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    <title>FPGA on icysamon&#39;s blog</title>
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      <title>Verilog - モジュールのインスタンス化とシグナル接続</title>
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      <title>Verilog - ベクトルのエックスノア (XNOR)</title>
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      <pubDate>Sun, 10 Dec 2023 14:27:00 +0900</pubDate>
      
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      <title>Verilog - for ループ</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-for-loop/</link>
      <pubDate>Sat, 09 Dec 2023 14:21:00 +0900</pubDate>
      
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      <title>Verilog - ビット演算子と論理演算子</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-bitwise-and-logical-operators/</link>
      <pubDate>Thu, 07 Dec 2023 14:44:00 +0900</pubDate>
      
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      <title>Verilog - ベクトルの分割</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-vector-split/</link>
      <pubDate>Wed, 06 Dec 2023 18:32:00 +0900</pubDate>
      
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      <title>Verilog - ベクトル</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-vector/</link>
      <pubDate>Wed, 06 Dec 2023 14:15:00 +0900</pubDate>
      
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      <title>Verilog - 7458チップ</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-7458-chip/</link>
      <pubDate>Wed, 06 Dec 2023 13:21:00 +0900</pubDate>
      
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      <title>Verilog - 点灯</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-led-on/</link>
      <pubDate>Tue, 05 Dec 2023 14:05:00 +0900</pubDate>
      
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      <title>Verilog - クロック信号</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-clock-signal/</link>
      <pubDate>Mon, 04 Dec 2023 14:06:00 +0900</pubDate>
      
      <guid>https://blog.icysamon.com/posts/2023/12/verilog-clock-signal/</guid>
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      <title>Verilog - 初めてのシグナル</title>
      <link>https://blog.icysamon.com/posts/2023/12/verilog-first-signal/</link>
      <pubDate>Mon, 04 Dec 2023 14:01:00 +0900</pubDate>
      
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